Paper Presented in Seminar

1Mr. Virendra Singh Rathore12/27/2012SAIT“Implantation of Real time DSP processes with FPGA in laboratory”
2Mr. Virendra Singh Rathore12/27/2012SAIT“FPGA implementation of Switching system using VHDL”
3Mr. Virendra Singh Rathore12/27/2012SAIT32 bit single precision floating point adder”
4Mr. Virendra Singh Rathore12/27/2012CSNT“High Speed power factor measurement using ASIC"
5Mr. Rupesh Dubey9/20/2012IEEE WOCN 2012.”“Performance Analysis of WiMAX 802.16e Physical Layer Model”
Copyright © 2012 IES, IPS Academy. All Rights Reserved.